Cadence introduces Maestro AI models for chip design workflows
The models are tailored to chip-design agents, with early access planned for selected customers in the fourth quarter of 2026. RuntimeWire reports that Cadence claims up to five times the token efficiency, but has not identified the comparison model or explained the measure behind a 30% quality figure.
- The models also target system-design workflows, according to Forbes.
Covered by 3 publishers within 3 hours of the first report.
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Tom's Hardware Cadence reveals Maestro, fine-tuned AI models built to run specialized chip design agents, with early access coming for 'select customers' in Q4 2026 · Shane Downing
RuntimeWire Cadence launches Maestro, which it says offers up to 5x token efficiency for chip-design agents · Ryan Merket
Forbes Cadence Ups Its Agentic Game With Maestro Domain-Specific AI Model · Karl Freund, Contributor